Minecraft Wiki

除另有声明,转载时均必须注明出处若簡繁轉換出錯,請以遊戲內為準请勇于扩充与修正内容有兴趣逛逛我们的微博沟通交流,欢迎到社区专页需要协助,请在告示板留言

了解更多

Minecraft Wiki
Advertisement
翻譯者從英文條目翻譯下文中的內容時感覺其艱澀難懂。

翻譯者希望更有能力的使用者能夠幫助改善本條目的行文,所以請先慎重對待本條目內容。
如果可能,請幫助我們完善此條目的內容。

Template:Mcrs diagrams

Brush
該文章需要整理以符合格式指導 討論

請幫助最佳化文章格式來讓它符合格式指導。

Adders(加法器)

Version 1

Full adder 4 wide-ingame

In-game screenshot of the Full Adder(全加器的遊戲截圖)

Full Adder(全加器)

A full adder takes two inputs A and B and a Carry input and produces the Sum and Carry outputs. It relies on two XOR gates, two AND gates, and one OR gate. With some thought, these gates can be compressed (as both AND and XOR gates already exist in the game , and an OR gate can simply be a redstone wire).

一個全加器接受兩個輸入位A、B以及一個來自低位的進位,並輸出一位和以及向高位的進位。它依賴於2個異或門,2個與門和1個或門。經過一些方面的考慮後,這些邏輯門結構可以被壓縮。

A and B are the bit inputs and C' is the carry in. It produces a sum at S and a carry out at C. When full adder modules are tiled together C' and C will be connected, which allows the carry to propagate to the next module.

如圖,A、B是兩個輸入位且C'是來自低位的進位。它產生一個和(S)以及向高位的進位(C)。當多個全加器單元連接在一起時,將下一個全加器的C'和目前全加器的C連接起來,以便產生的進位能夠向高位傳遞。

Half Adder(半加器)

The half adder is nearly identical to the full adder, except the second XOR gate is removed and the output from the first XOR gate becomes S. There is no carry in (C'), but the carry out (C) circuit is still on top of the first XOR gate and provides a carry to the first full adder. Some ALUs will not use a half adder for the first bit, to support INCREMENT(increment)(allow a carry in on the first bit).

半加器和全加器幾乎相同,但沒有第二個異或門並且直接從第一個異或門輸出和(S)。它沒有來自低位的進位(C'),但向高位的進位(C)仍然在第一個異或門頂端且向第一個全加器產生一個進位。有的運算器不使用半加器作為第一位,以支持增量(允許向第一位進位)。

編輯手冊

In-Line Adder(單列版加法器)

Full Adder條例
Full adder 2 wide-ingame

In-game screenshot of the 2 wide Full Adder(2格寬全加器的遊戲截圖)

This full adder is similar to the previous one, except for the fact that it is two wide and the inputs are aligned vertically. This design is great for minimizing horizontal space and can be built in-line with two redstone buses, eliminating the space required to expand a bus to reach the inputs of a wider full adder.

這種全加器相似於上面的那種,除了事實上它兩格寬且易於對齊。這樣的設計對於最小化水平空間是相當有用的,而且可以被成列地建造並接入兩條紅石總線,消除因擴張總線以接入擴大規模的加法器(的要求)致浪費的空間。

Version 2

Full Adder

Gates: XNOR (同或門)(2), IMPLIES(蘊涵門), NOT(非門), OR(或門), AND (與門)
Size: 6×12×5 (including I/O spaces)(包括輸入輸出空間)

This adder will take 2 bits and a carried over bit (actually C, rather than C(事實上是C頂加槓而非C), a value held(保留值) in the redstone in the bottom left corner (底層左邊角落)on layer 1) (第1層)and add them all together, producing a sum (S) bit and a carry (actually C rather than C).

這個加法器將取2個輸入位A、B和1個低位的進位C(事實上是C的否定C而並非是C,即示意圖中Layer 1左下角紅石端的訊號值)並將它們相加,產生一個和位(S)和一個向高位的進位(這裡同樣是C的否定C而並非是C)。

When using the gates above; mind the inputs and outputs. You may be wondering why there are so many inverted signals being used instead of the regular (規則的)signal.

使用上述的邏輯門時,請注意輸入和輸出。您可能想知道為什麼有那麼多反相的訊號位用以代替常規的訊號位。

The adders shown here use XNOR gates rather than XOR gates because they are more compact(緊湊的), and as a result, implies gates must be used instead of AND gates, which also happen to be more compact.

上述加法器使用了同或門而不是異或門,因為這樣設計更加緊湊。同理,我們使用蘊含門來代替與門,這樣能夠更加緊湊。

Therefore for the most compact adder, inverse signals must be used. These adders are too complex(複雜的) to be easily deciphered(破譯) with 2 layers per square, so each single layer has been drawn separately(分開地) to ease the building process.

因此對於(結構)最緊湊的加法器,必然要使用反相的訊號。這些加法器太複雜,很難用(每格可以容納2層的)平面圖來表示,所以將每一層都單獨表示為一張示意圖以使建造過程更加清晰易懂。

Half Adder(半加器)

Gates: XNOR(同或門), IMPLIES(蘊含門)
Size: 5×4×4

This adder will take 2 bits and add them together. The resulting bit will be the output of S (sum). If both bits are 1, there will be a carry over, and C will become 1 (C will become 0). This half adder can be modified to create a non inverted C output, but this configuration is used so that it can be implemented as the start of a chain of full adders.

這個加法器將2個輸入位相加得到結果作為和輸出(S)。如果2個輸入位的訊號值都是1,進位C將會得到1(C將會是0)。可以對這個半加器進行修改來獲得一個非反相的輸出C,但使用這個半加器才能作為一個全加器鏈(多位全加器)的起始部分。

Extension(延伸:(活塞)門的控制,使你的門能從內部反鎖): for those new to advanced redstone like myself, it's easier to understand it like this: let's say output B (C) has a NOT gate that inverts the signal and it leads to an iron door or piston door etc. Output A (S) is connected to sticky pistons controlling the floor. Let's say for sake of argument that there is 1×1×1 block NOT affected by the sticky pistons, this is the safety block. When you activate input A, both the door will open and the floor will drop, if you're standing on the safety block, then you will not fall. Input B will control only the floor, but if input A is on the input B will control them both. When both are on, input A will only affect the floor. This means if you are off the server and want no one in, leave A and B on, when they deactivate A, the floor will drop, but the door will stay closed, so if they know the secret, they still cannot get in.

對於剛接觸紅石的人來說,這樣更容易理解:我們說輸出位C有一個非門將訊號反相併連接到一個鐵門、活塞門之類的門,輸出位S連接到一些粘性活塞來控制地面陷阱。假設有一個1×1×1的方塊不受粘性活塞影響,稱之為安全方塊。當輸入位A有紅石訊號時,門打開的同時,地面也會打開,如果你站在安全方塊上,你就不會掉下去。輸入位B只控制地面,但如果輸入位A有紅石訊號,則輸入位B會同時控制這二者。(同理)當兩個輸入位都有紅石訊號時,輸入位A只控制地面。這意味著如果你離開伺服器的時候不想讓任何人進來,你可以給輸入位A和B加上紅石訊號,當其他人移除輸入位A的紅石訊號時,地面會打開,但門依然是關閉的。即使他們知道這個秘密也仍然不能進來。

Version 3

Full Adder(全加器)

Size: 5×6×3

Carry input and output are aligned to easily connect many of these modules in series.

每位進位都是相互對齊的,這樣可以方便地串聯這些子模組。

Fast Adding(快速加法器)

When building advanced digital circuits like computers and multipliers, the adders used must be as fast as possible to ensure maximum running speed. Simple adders have one fundamental speed problem which numerous adder designs try to correct to speed up. The issue is carry propagation delay: delay caused by the way adders borrow carries. We can see this when we do the problem 1111 + 0001:

當建造高級數字電路比如計算機和乘法器時,使用的加法器必須儘可能地快,以確保最大的執行速度。簡單的加法器存在一個基本的速度問題,許多加法器設計都嘗試改善這一問題。這個問題是進位傳播的延遲,這是由加法器的進位方式所引起的延遲。我們可以看如下的例子:

1111
0001
----
1110

This is the first step of the addition process, XORing the two inputs. Because there were two 1s in the least significant bit, the AND gate activates and carries to the next bit:

這是加法運算過程的第一步,對兩個輸入異或。由於最低有效位有兩個1,這會觸發與門產生進位並送往高位:

  1
1111
0001
----
1100

But here is the issue: You now need to borrow a carry again, because, in the two's place, there are two ones. This is done by ANDing the output of the first half-adder with the carry from the previous bit and this is a huge issue. Because, for the next bit, you AND the borrowed carry again, and again. Each AND gate takes 2 ticks, so, in order to calculate all of the carries that need to be added up in the final step, it takes 2 ticks times 4 bits, or 8 ticks.

此時就產生了問題:由於待進位的目前位上仍然有兩個1,所以會再次觸發向高位的進位。這是透過將第一個半加器的輸出與低位的進位相加來完成的,這裡存在很大的問題,因為接下來你將反覆產生向高位的進位直到越過最高位。如果每個與門產生2刻的延遲,為了計算最後一步中需要相加的所有進位,總共需要2刻×4,即8刻的時間。

Imagine you see the problem 999 + 1. You don't sit around thinking "9 + 1 is 10, carry 1, so 9 + 1 is 10, carry the 1, so 9 + 1 is 10, so 1000." It's the same situation in an advanced circuit.

如果現在你要計算999+1,你不會有「9 + 1 = 10,進位1,所以9 + 1 = 10,進位1,所以9 + 1 = 10,得到1000」這種閒得無聊的想法。在高級電路中同樣也是如此。

Real electrical engineers and creative redstoners have designed circuits that calculate adder carries faster than this sequential method.

真正的電路工程師和有創造力的紅石玩家已經設計出了計算進位比這種串行方式更高效的電路。

Incidentally, adders that calculate carries one at a time in this fashion are called Ripple Carry adders(連鎖進位加法器,又譯作行波進位加法器).

順便提一下,以這種串行方式計算進位的加法器被稱為行波進位加法器

Piston Adders(活塞無延加法器)

One of the simplest and most classic ways of solving the ripple carry problem is to use instant AND gates that use pistons. These adders are simple and fast, but are inconstant because they use pistons. When blocks are accidentally dropped, the entire circuit breaks. Pistons also have timing awkwardness that can be excruciatingly inconvenient when building an advanced circuit that relies heavily on timing.

解決行波進位存在的問題的最簡單、最經典的方法之一是使用帶活塞的即時與門。這種加法器簡單快速,但由於使用活塞導致電路不穩定,當方塊因意外而掉落時,整個電路就被破壞了。活塞也存在時鐘同步上可能難以忍受的不便之處,在建造高級電路時可能會對(整個裝置)的同步時鐘產生嚴重依賴性。

PistonANDgates

Whenever a carry is created, it is sent through the wire with the lever on it, and, instead of going through an AND gate, the piston retracts and the carry can move on to the next bit which adds no carry propagation delay at all (until the signal strength runs out).

每當產生進位時,其將會透過帶控制桿的紅石線路傳送,而不是與門。活塞收縮,進位C被送到高位,這一過程完全沒有產生進位傳播的延遲(直到訊號強度耗盡)。

This video shows a straightforward implementation of the logic. The design is large and spread out, so it's easy to see each individual part of the adder and the carry logic.

下面這個影片展示了這種邏輯的一個簡單實現。這種設計龐大而且分散,容易看到每一個單獨的加法器部分以及進位邏輯。


4-bit Adder(4位加法器)

Gates: XNOR (7), IMPLIES (4), NOT (4), OR (3), AND (3)
Size: 23X12X5

Note! The least significant digit ("ones" digit) is on the left of the diagram so that the progression from half adder to the full adders can be seen more clearly. Reverse the diagram if you want a conventional left to right input.

注意!最低有效位(個位)在圖的左邊,這樣可以更清楚地看到從半加器到全加器的過程。如果想要通常的從左向右的輸入,請翻轉示意圖。

This adder will take 2, 4 bit numbers (A and B) and add them together, producing a sum (S) bit for each bit added and a carry (C) for the whole sum. The sum bits are in the same order as the input bits, which on the diagram means that the leftmost S output is the least significant digit of the answer. This is just an example of a string of adders; adders can be strung in this way to add bigger numbers as well.

這個加法器將第2、第4位的輸入位(A和B)相加,每加1位產生一個和(S)以及一個進位(C)。和的順序與輸入位順序相同,這意味著圖中最左邊的輸出位S代表結果的最低有效位。這是一個多位加法器的例子;加法器可以透過這種方式串聯起來以計算更多位數的數字。

Alternate(交替式) 4-bit Adder

The same function but a different design with 4 full adders instead of 1 half adder and 3 full adders.

功能相同但設計不同,使用4個全加器而不是1個半加器和3個全加器。

NOTE: switches are inputs A and B (top switch C input)

注意:開關為輸入位A和B(頂部為低位進位C)。

Subtracting(減法)

Subtracting and adding are the same thing when reduced down to the idea that, for example, 3-2 = 3 + (-2) = 1. Since we already have the framework in place to add bits, it is fairly simple to subtract by just adding the negative bit.(減去一個數等於加上這個數的相反數) The problem lies in the representation of negative numbers.(問題在於如何描述負數)

減法和加法的道理是一樣的,例如,3 - 2 = 3 + (-2) = 1。因為我們已經有了加法計算的框架,只需要加入一個負號就可以簡單地得到結果。問題在於如何表示這個負數。

We are all familiar with the elementary school concept of "borrowing" in subtraction from the next column like this:

我們對小學(原文為基礎學校)的減法(向高位)借位概念很熟悉,比如這樣:

 5623
- 128
-----

We are not capable of taking 8 from three, so we "borrow" a 1 from the next decimal place to allow us to subtract 8 from 13 instead .(resulting in 5)

我們沒有辦法用3減去8,所以我們從高一位借了1以透過13減8代替(結果顯然是5)。

   1
 5623
- 128
-----
    5

Computers are not capable of assumptions(電腦沒法考慮), so when a computer needs to find a negative it does not (and cannot) put a negative sign in front of the input. It just subtracts from zero "borrowing" from the next column like so:(以這種思路,電腦的預設進位問題可能導致運算錯誤)

然而計算機是沒法做這種考慮的,所以當計算機找到一個負數時,它不會也不能在前面硬添一個負號。它只會像如下這樣從高位進行"借位"相減:

 000000
 -    3
-------
-999997

This is the same in binary. Let us, for example use a 4 bit binary number for the example:

這在二進制中同樣適用。讓我們用一個4位二進制數作為例子:

   1      11     111    1111
 0000    0000    0000    0000
-0011   -0011   -0011   -0011
-----   -----   -----   -----
-   1   -  01   - 101   -1101

We could repeat this forever, but that would be useless(無用的). This is about what a 4 bit register(表示法) does: it truncates(截斷) after 4 bits worth of data. So after we truncate the number (which I kindly did for you in the example, otherwise(別處的) the number would have an infinite(無窮的) number of 1's to the left). Thanks to this little perk, we can do whatever we want to the 0's after the four of them, including (which will prove to be fantastically useful later) adding a single 1 in front of them.

我們可以按照這個方式一直反覆計算下去,但這並沒有什麼用。這就體現了4位寄存器的作用:它將在接收到4位資料後截斷(拋棄其他資料)。因此,在我們截斷這個數字之後(在這個例子中已經得到了體現,否則最後結果的左邊會有無窮多個1),多虧這個小技巧,我們可以對這4位資料之外的0做任何想做的事情,包括在它們之前添一個1(這將在之後被證明是非常有用的)。

10000
-0011
-----
 1101 <-- NOTE: This number is positive! Success!(注意:这个数字是正数!成功!)

Remember how we said that our redstone had no special way of designating a negative from a positive? We just created a way. If the most significant(符號資料) (first) bit of a number is 1 that means that it is a negative number. This fantastic perk of binary numbers is a theorem called "Two's Complement".

還記得我們說過我們的紅石沒有特別的方法來區分正數和負數嗎?我們只是創造了一種區分的方式:如果數字的符號位(最高位)是1,那麼它就是一個負數。這種利用在二進制數中的小技巧其實是一套名為「二進制補碼」的理論。

Formally, Two's Complement is defined as:

二進制補碼的正式定義是:

The negative of a number b with bit length n is equal to 2^(n+1) - b

一個負數b的補碼等於2 ^ (n+1) - b,其中n是b的位數。

Essentially what this is saying is that -b is just the inversion of b (exchange 1's for 0's and 0's for 1's) plus 1.

本質上說,-b的補碼就是將b的補碼的各位取反(用1替換0,用0替換1)再加1。


What we have done is turn the first bit into a "negative sign" if it is on, but if you have been reading this you realize it is not that simple. Numbers that have a negative sign like this are commonly referred to as signed integers(像這樣有符負號的數字通常被歸類到帶符號的整數(即整型int)).

我們所做的是將最高位變成一個"負號"(如果它是1),但如果你一直在閱讀這個頁面,你會意識到這沒有那麼簡單。通常把帶有這種符號標識位的數字稱為帶符號的整數。

Numbers like in a normal adder, where two's compliment is not taken into effect are called unsigned integers. Unsigned integers can go to a higher value, but cannot go below zero where as signed integers can only go half as high, but they can go equally as far below zero.


在普通的加法器中,這種二進制補碼規則並不生效,這種數字稱為無符號的整數。無符號的數字可以比帶符號的數字取到更大的值,但不能比0小;帶符號的數字最大只能取到無符號數字所能取到的大約一半,但可以比0小。

This means that the two numbers have the same range, it is just in a different location like so (this is with an 8 bit number):

Unsigned: 0-255
Signed (-128)-127

這意味著這兩種數字有相同長度的取值範圍,但取值區間的位置不同,比如下面的8位元整數的例子:

无符号: 0 - 255
带符号:-128 - 127

It should be noted that some strange effects can take place when using the lowest signed value (in this case -128) so this should be avoided. 應當注意的是,當使用最小的有符號數(在上面的例子中是-128)時,可能會出現一些匪夷所思的問題,所以應該避免這種情況。

Now that we have a positive way of representing our negative numbers it is very trivial to implement this into an adder. Currently our adder solves 現在我們有了一種用正的值來表示負數的方法,將它運用到加法器中就很簡單了。目前我們可以計算

A + B

We want it to solve 我們希望解決

A - B

or 即

A + (-B)

Therefore, if we enter the two's complement of B, our adder becomes a subtractor. (減數變補碼,減法化加法)This is easily implemented by using the Carry-in bit of the least significant (first) bit as the "+1" and then all that is left is to invert B. 所以,只要我們輸入B的補碼,加法器就變成了減法器。透過使用符號位(最高位)作為進位的1,這很容易實現。剩下的就是如何對B求補碼。

There is one important thing to note when implementing this. Because it is possible to get a two's complement number out, when subtracting the most significant digit must be inverted. This is usually the Carry out of the last adder. 在實現此功能時需要注意一件重要的事情:因為得到的結果依然是二進制補碼,所以存在減去符號位的問題,因此要倒過來減。這個問題通常由最高位的加法器來處理。

This can all be implemented into an adder like so:

這都可以實現到一個加法器中:

Addsub

A control bit is added to the circuit such that when it is on, the unit subtracts, and when it is off the unit adds. After this, add XOR gates between the control bit and each B input. Route the output of each XOR to the B input of each adder. Finally, to make the unit Two's compliment compatible, a final XOR gate must be added between the control bit and the carry out of the most significant bit. 電路中加入了一個控制位,當它被通入紅石訊號時,就會變成一個減法器,當沒有紅石訊號時則是一個加法器。此外,在控制位和輸入B的每一位之間都增加了一個異或門,將每個異或門的輸出作為每個加法器單元真正的輸入位B。最後,為了使二進制補碼單元相容,需要在控制位和符號位上加入最後一個異或門。

This is the simplest way to implement negatives and subtraction in a CPU, as it will add gracefully and store well in registers. If this is to be implemented in a calculator, simply subtract 1 from the output and then invert all the outputs except the most significant one. The most significant bit will be on if the number is negative.

這是在CPU中實現負數和減法的最簡單方法,因為它可以優雅地進行加法運算並將結果儲存在寄存器中。如果需要在計算器中實現這種操作,只需要將輸出結果減1,然後將符號位之外的每一位取反。如果數字是負數,只需要將符號位設為1即可。


原文:In order to make a subtracter(減法器), simply invert(取反) one of the binary(二進制) inputs (the 1st or 2nd number)(第1或2個數字,反正是減數而不是被減數). If the number is negative(是負數), the answer comes out inverted(被減數與減數對調再加負號). In real computers, the first bit (also called the sign(符號位)) decides whether the number is positive or negative(是正還是負), if you include(考慮/計入) this (applying(應用) the same inverting rule(取反規則)) you can detect(察覺/發現) whether the number is negative, or if it is just a big number.

問題:出現了±0的情況,導致0有兩個輸出法

Logic units(邏輯單元)

In circuits, it might be useful to have a logic unit that will, based on the input, decide which output is to be chosen. 在電路中使用一個邏輯單元可能是有用的。邏輯單元會根據控制訊號來決定輸出哪種操作的結果。 Such a unit can then be used for more complex circuits, such as an ALU. 這樣的邏輯單元可以使用在更加複雜的電路中,比如ALU(算術邏輯單元)。

This is an example of a 2-bit logic unit that will have four states depending on the input. 這是一個2位邏輯單元的例子,它的控制訊號有4種狀態。

Logic unit

The outputs are in top row, with 11, 00, 01, 10 order (input order: first first, bottom second). 它的輸出在最上面一行,從左到右依次透過輸入11、00、01和10來觸發(輸入在左邊,上面是低位,下面是高位)

This is another example of a simplified version using Gray codes. The output appears at the torches at the end of the top rows. This design can be extended to any number of bits, but practical limitations due to timing considerations restrict the use of more than a byte or so. The outputs are triggered by the inputs 11, 01, 00, 10, respectively. 這是另一個使用格雷碼的簡化版本,輸出體現在最上面一行紅石火把的亮滅。這種設計可以擴展到任意的位數,但考慮到時間效率的問題,一般不會超過1個字節(8位元)。輸出從左到右依次透過輸入11、01、00、10來觸發。

Logic unit 3

Arithmetic logic unit (ALU)(算術邏輯單元)

ALUwikipedia

The Arithmetic logic unit (ALU) is the central part of the CPU. It does calculations and logical processing and then passes this information to a register. The ALU, on basis of the input, selects a specific function, performs it, and then gives the result. 算術邏輯單元(ALU)是CPU的核心部分。它進行計算和邏輯處理,然後將結果傳遞給寄存器。ALU根據輸入來選擇一個特定的運算操作,執行它,然後給出結果。

The ALU shown below is a 1-bit ALU with the functions: ADD, AND, XOR. It takes the A and B inputs and then performs the selected functions. Read about the adders to see how the ADD function works. XOR and AND are basic functions that are explained on the logic circuits page. 下圖顯示的ALU是一個1位的ALU,可以執行下列運算:ADD(求和),AND(求與),XOR(求異或)。它接收輸入A和B,然後執行所選擇的運算操作。閱讀加法器以了解ADD運算是如何工作的。XOR和AND運算是在邏輯電路頁面上所介紹的基本功能。 There can be more functions added to an ALU, like multiplication, division, OR, NAND... etc. These functions could, with some modifications, be added to this 1 bit ALU. 可以向ALU中加入更多的運算操作,比如乘法,除法,OR(求或),NAND(求與非)等等,這些運算都可以透過對ALU進行一定的修改來加入到其中。

This 1-bit ALU can be linked to each other to create an as many bit ALU as possible. Just like adders you need to connect the Carry out (Cout) to the Carry in (Cin) of the next ALU 這樣的1位ALU可以相互連接起來以形成多位的ALU。就像加法器一樣,把示意圖中的C out端連接到另一個ALU的C in端即可。

Advertisement