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Adders(加法器)

Version 1

Full adder 4 wide-ingame

In-game screenshot of the Full Adder(全加器的游戏截图)

Full Adder(全加器)

A full adder takes two inputs A and B and a Carry input and produces the Sum and Carry outputs. It relies on two XOR gates, two AND gates, and one OR gate. With some thought, these gates can be compressed (as both AND and XOR gates already exist in the game , and an OR gate can simply be a redstone wire).

一个全加器接受两个输入A、B以及一个来自低一位的进位(下简称C')并产生和(一位,下简称S)与向高一位的进位(下简称C)且输出。它凭借(依靠)2个异或门,2个与门和1个或门。经过思考后,这些门部件可以被压缩(例子内容不会翻,利用好教程/基本逻辑门词条)。

A and B are the bit inputs and C' is the carry in. It produces a sum at S and a carry out at C. When full adder modules are tiled together C' and C will be connected, which allows the carry to propagate to the next module.

图注:A、B是位运算输入且C'是来自低位的进位。它产生一个和(S)并向高位进位(C)。当全加器作为一个模块(利用结构方块)时,可以考虑平铺多个模块以允许本位的C与高一位的C(下一个模块的)直接连接。

Half Adder(半加器)

The half adder is nearly identical to the full adder, except the second XOR gate is removed and the output from the first XOR gate becomes S. There is no carry in (C'), but the carry out (C) circuit is still on top of the first XOR gate and provides a carry to the first full adder. Some ALUs will not use a half adder for the first bit, to support INCREMENT(increment)(allow a carry in on the first bit).

半加器和全加器几乎相同,但没有第二个异或门并且直接从第一个异或门输出和(S)。它没有来自低一位的进位(C'),但向高一位的进位(C)仍然在第一个异或门顶端且向第一个全加器产生一个进位。有的运算器(ALU)不使用半加器作为第一位,以支持增量(允许向第一位进位)。

编辑手册

In-Line Adder(单列版加法器)

Full Adder条例
Full adder 2 wide-ingame

In-game screenshot of the 2 wide Full Adder

This full adder is similar to the previous one, except for the fact that it is two wide and the inputs are aligned vertically. This design is great for minimizing horizontal space and can be built in-line with two redstone buses, eliminating the space required to expand a bus to reach the inputs of a wider full adder.

这种全加器相似于上面提供的,除了事实上它两格宽且易于对齐。这样的设计对于最小化水平空间是相当有用的,而且可以被成列地建造并接入两条红石总线,消除因扩张总线以接入扩大规模的加法器(的要求)致浪费的空间。

Version 2

Full Adder

Gates: XNOR (同或门)(2), IMPLIES(蕴涵门), NOT(非门), OR(或门), AND (与门)
Size: 6×12×5 (including I/O spaces)(包括输入输出空间)

This adder will take 2 bits and a carried over bit (actually C, rather than C(事实上是C顶加杠而非C), a value held(保留值) in the redstone in the bottom left corner (底层左边角落)on layer 1) (第1层)and add them all together, producing a sum (S) bit and a carry (actually C rather than C).

这个加法器将取2个输入位A、B和1个低位的进位C(事实上是C的否定C而并非是C,即示意图中Layer 1左下角红石端的信号值)并将它们相加,产生一个和位(S)和一个向高位的进位(这里同样是C的否定C而并非是C)。

When using the gates above; mind the inputs and outputs. You may be wondering why there are so many inverted signals being used instead of the regular (规则的)signal.

使用上述的逻辑门时,请注意输入和输出。您可能想知道为什么有那么多反相的信号位用以代替常规的信号位。

The adders shown here use XNOR gates rather than XOR gates because they are more compact(紧凑的), and as a result, implies gates must be used instead of AND gates, which also happen to be more compact.

Therefore for the most compact adder, inverse signals must be used. These adders are too complex(复杂的) to be easily deciphered(破译) with 2 layers per square, so each single layer has been drawn separately(分开地) to ease the building process.

因此对于(结构)最紧凑的加法器,必然要使用反相的信号。这些加法器太复杂,很难用(每格可以容纳2层的)平面图来表示,所以将每一层都单独表示为一张示意图以使建造过程更加清晰易懂。

Half Adder(半加器)

Gates: XNOR(同或门), IMPLIES(蕴含门)
Size: 5×4×4

This adder will take 2 bits and add them together. The resulting bit will be the output of S (sum). If both bits are 1, there will be a carry over, and C will become 1 (C will become 0). This half adder can be modified to create a non inverted C output, but this configuration is used so that it can be implemented as the start of a chain of full adders.

这个加法器将2个输入位相加得到结果作为和输出(S)。如果2个输入位的信号值都是1,进位C将会得到1(C将会是0)。可以对这个半加器进行修改来获得一个非反相的输出C,但使用这个半加器才能作为一个全加器链(多位全加器)的起始部分。

Extension(延伸:(活塞)门的控制,使你的门能从内部反锁): for those new to advanced redstone like myself, it's easier to understand it like this: let's say output B (C) has a NOT gate that inverts the signal and it leads to an iron door or piston door etc. Output A (S) is connected to sticky pistons controlling the floor. Let's say for sake of argument that there is 1×1×1 block NOT affected by the sticky pistons, this is the safety block. When you activate input A, both the door will open and the floor will drop, if you're standing on the safety block, then you will not fall. Input B will control only the floor, but if input A is on the input B will control them both. When both are on, input A will only affect the floor. This means if you are off the server and want no one in, leave A and B on, when they deactivate A, the floor will drop, but the door will stay closed, so if they know the secret, they still cannot get in.

对于刚接触红石的人来说,这样更容易理解:我们说输出位C有一个非门将信号反相并连接到一个铁门、活塞门之类的门,输出位S连接到一些粘性活塞来控制地面陷阱。假设有一个1×1×1的方块不受粘性活塞影响,称之为安全方块。当输入位A有红石信号时,门打开的同时,地面也会打开,如果你站在安全方块上,你就不会掉下去。输入位B只控制地面,但如果输入位A有红石信号,则输入位B会同时控制这二者。(同理)当两个输入位都有红石信号时,输入位A只控制地面。这意味着如果你离开服务器的时候不想让任何人进来,你可以给输入位A和B加上红石信号,当其他人移除输入位A的红石信号时,地面会打开,但门依然是关闭的。即使他们知道这个秘密也仍然不能进来。

Version 3

Full Adder(全加器)

Size: 5×6×3

Carry input and output are aligned to easily connect many of these modules in series.

进位相互对齐以方便连接多个次模块

Fast Adding(快速加法器)

When building advanced digital circuits like computers and multipliers, the adders used must be as fast as possible to ensure maximum running speed. Simple adders have one fundamental speed problem which numerous adder designs try to correct to speed up. The issue is carry propagation delay: delay caused by the way adders borrow carries. We can see this when we do the problem 1111 + 0001:

当建造高级数字电路比如计算机和乘法器时,使用的加法器必须尽可能地快,以确保最大的运行速度。简单的加法器存在一个基本的速度问题,许多加法器设计都尝试改善这一问题。这个问题是进位传播的延迟,这是由加法器的进位方式所引起的延迟。我们可以看如下的例子:

1111
0001
----
1110

This is the first step of the addition process, XORing the two inputs. Because there were two 1s in the least significant bit, the AND gate activates and carries to the next bit:

这是加法运算过程的第一步,对两个输入异或。由于最低有效位有两个1,这会触发与门产生进位并送往高位:

  1
1111
0001
----
1100

But here is the issue: You now need to borrow a carry again, because, in the two's place, there are two ones. This is done by ANDing the output of the first half-adder with the carry from the previous bit and this is a huge issue. Because, for the next bit, you AND the borrowed carry again, and again. Each AND gate takes 2 ticks, so, in order to calculate all of the carries that need to be added up in the final step, it takes 2 ticks times 4 bits, or 8 ticks.

此时就产生了问题:由于待进位的当前位上仍然有两个1,所以会再次触发向高位的进位。这是通过将第一个半加器的输出与低位的进位相加来完成的,这里存在很大的问题,因为接下来你将反复产生向高位的进位直到越过最高位。如果每个与门产生2刻的延迟,为了计算最后一步中需要相加的所有进位,总共需要2刻×4,即8刻的时间。

Imagine you see the problem 999 + 1. You don't sit around thinking "9 + 1 is 10, carry 1, so 9 + 1 is 10, carry the 1, so 9 + 1 is 10, so 1000." It's the same situation in an advanced circuit.

如果现在你要计算999+1,你不会有“9 + 1 = 10,进位1,所以9 + 1 = 10,进位1,所以9 + 1 = 10,得到1000”这种闲得无聊的想法。在高级电路中同样也是如此。

Real electrical engineers and creative redstoners have designed circuits that calculate adder carries faster than this sequential method.

真正的电路工程师和有创造力的红石玩家已经设计出了计算进位比这种串行方式更高效的电路。

Incidentally, adders that calculate carries one at a time in this fashion are called Ripple Carry adders(连锁进位加法器,又译作行波进位加法器).

Piston Adders(活塞无延加法器)

One of the simplest and most classic ways of solving the ripple carry problem is to use instant AND gates that use pistons. These adders are simple and fast, but are inconstant because they use pistons. When blocks are accidentally dropped, the entire circuit breaks. Pistons also have timing awkwardness that can be excruciatingly inconvenient when building an advanced circuit that relies heavily on timing.

PistonANDgates

Whenever a carry is created, it is sent through the wire with the lever on it, and, instead of going through an AND gate, the piston retracts and the carry can move on to the next bit which adds no carry propagation delay at all (until the signal strength runs out).

This video shows a straightforward implementation of the logic. The design is large and spread out, so it's easy to see each individual part of the adder and the carry logic.


4-bit Adder

Gates: XNOR (7), IMPLIES (4), NOT (4), OR (3), AND (3)
Size: 23X12X5

Note! The least significant digit ("ones" digit) is on the left of the diagram so that the progression from half adder to the full adders can be seen more clearly. Reverse the diagram if you want a conventional left to right input.

This adder will take 2, 4 bit numbers (A and B) and add them together, producing a sum (S) bit for each bit added and a carry (C) for the whole sum. The sum bits are in the same order as the input bits, which on the diagram means that the leftmost S output is the least significant digit of the answer. This is just an example of a string of adders; adders can be strung in this way to add bigger numbers as well.

Alternate(交替式) 4-bit Adder

The same function but a different design with 4 full adders instead of 1 half adder and 3 full adders

NOTE: switches are inputs A and B (top switch C input)

Subtracting(减法)

Subtracting and adding are the same thing when reduced down to the idea that, for example, 3-2 = 3 + (-2) = 1. Since we already have the framework in place to add bits, it is fairly simple to subtract by just adding the negative bit.(减去一个数等于加上这个数的相反数) The problem lies in the representation of negative numbers.(问题在于如何描述负数)

We are all familiar with the elementary school concept of "borrowing" in subtraction from the next column like this:

我们对小学(原文为基础学校)的减法(向高位)借位概念很熟悉,比如这样:

 5623
- 128
-----

We are not capable of taking 8 from three, so we "borrow" a 1 from the next decimal place to allow us to subtract 8 from 13 instead .(resulting in 5)

我们没有办法用3减去8,所以我们从高一位借了1以通过13减8代替(结果显然是5)

   1
 5623
- 128
-----
    5

Computers are not capable of assumptions(电脑没法考虑), so when a computer needs to find a negative it does not (and cannot) put a negative sign in front of the input. It just subtracts from zero "borrowing" from the next column like so:(以这种思路,电脑的默认进位问题可能导致运算错误)

 000000
 -    3
-------
-999997

This is the same in binary. Let us, for example use a 4 bit binary number for the example:

   1      11     111    1111
 0000    0000    0000    0000
-0011   -0011   -0011   -0011
-----   -----   -----   -----
-   1   -  01   - 101   -1101

We could repeat this forever, but that would be useless(无用的). This is about what a 4 bit register(表示法) does: it truncates(截断) after 4 bits worth of data. So after we truncate the number (which I kindly did for you in the example, otherwise(别处的) the number would have an infinite(无穷的) number of 1's to the left). Thanks to this little perk, we can do whatever we want to the 0's after the four of them, including (which will prove to be fantastically useful later) adding a single 1 in front of them.

10000
-0011
-----
 1101 <-- NOTE: This number is positive! Success!

Remember how we said that our redstone had no special way of designating a negative from a positive? We just created a way. If the most significant(符号数据) (first) bit of a number is 1 that means that it is a negative number. This fantastic perk of binary numbers is a theorem called "Two's Complement".

Formally, Two's Complement is defined as:

The negative of a number b with bit length n is equal to 2^(n+1) - b

Essentially what this is saying is that -b is just the inversion of b (exchange 1's for 0's and 0's for 1's) plus 1.

正式的二进制补码定义:b的补码等于2^(n+1)-b,其中n是b的位数

实际上这意味着:b的补码是b的反码+1(本质是同模运算转化)

(辨析见https://www.cnblogs.com/zhangziqiu/archive/2011/03/30/ComputerCode.html解释与原理

https://www.cnblogs.com/anyehome/p/11111325.html速算法则)

What we have done is turn the first bit into a "negative sign" if it is on, but if you have been reading this you realize it is not that simple. Numbers that have a negative sign like this are commonly referred to as signed integers(像这样有符负号的数字通常被归类到带符号的整数(即整型int)).

Numbers like in a normal adder, where two's compliment is not taken into effect are called unsigned integers. Unsigned integers can go to a higher value, but cannot go below zero where as signed integers can only go half as high, but they can go equally as far below zero.

意译:无符号位的数第一位直接参与表示绝对值,这样的数字的绝对值值域是等长度有符号数的二倍,但是无法像有符号数字一样表示负数

This means that the two numbers have the same range, it is just in a different location like so (this is with an 8 bit number):

Unsigned: 0-255
Signed (-128)-127

意译:意思是那两个数字有着相同的浮动的范围,它就是在一个不一样的位置例如(这是一个附加的八位二进制数例子): 无符号位的:0-255(2^8-1) 有符号位的:(-128)-127 [即(-2^7)-(2^7-1)]

It should be noted that some strange effects can take place when using the lowest signed value (in this case -128) so this should be avoided. 意译:以避免一些奇怪的结果(如正负0)

Now that we have a positive way of representing our negative numbers it is very trivial to implement this into an adder. Currently our adder solves

A + B

We want it to solve

A - B

or

A + (-B)

Therefore, if we enter the two's complement of B, our adder becomes a subtractor. (减数变补码,减法化加法)This is easily implemented by using the Carry-in bit of the least significant (first) bit as the "+1" and then all that is left is to invert B.

There is one important thing to note when implementing this. Because it is possible to get a two's complement number out, when subtracting the most significant digit must be inverted. This is usually the Carry out of the last adder.

This can all be implemented into an adder like so:

Addsub

A control bit is added to the circuit such that when it is on, the unit subtracts, and when it is off the unit adds. After this, add XOR gates between the control bit and each B input. Route the output of each XOR to the B input of each adder. Finally, to make the unit Two's compliment compatible, a final XOR gate must be added between the control bit and the carry out of the most significant bit.

This is the simplest way to implement negatives and subtraction in a CPU, as it will add gracefully and store well in registers. If this is to be implemented in a calculator, simply subtract 1 from the output and then invert all the outputs except the most significant one. The most significant bit will be on if the number is negative.

注:尴尬的反码

原文:In order to make a subtracter(减法器), simply invert(取反) one of the binary(二进制) inputs (the 1st or 2nd number)(第1或2个数字,反正是减数而不是被减数). If the number is negative(是负数), the answer comes out inverted(被减数与减数对调再加负号). In real computers, the first bit (also called the sign(符号位)) decides whether the number is positive or negative(是正还是负), if you include(考虑/计入) this (applying(应用) the same inverting rule(取反规则)) you can detect(察觉/发现) whether the number is negative, or if it is just a big number.

问题:出现了±0的情况,导致0有两个输出法

Logic units(逻辑单元)

In circuits, it might be useful to have a logic unit that will, based on the input, decide which output is to be chosen. (通过输入改变输出,如[1,0][1,0]两个输入可输出[11,10,01,00]四个输出,以更好地控制,减少输入端个数) Such a unit can then be used for more complex circuits, such as an ALU.

This is an example of a 2-bit logic unit that will have four states depending on the input. (图示,平面版2位逻辑单元(通常把它们叠起来))

Logic unit

The outputs are in top row, with 11, 00, 01, 10 order (input order: first first, bottom second).

This is another example of a simplified version using Gray codes. The output appears at the torches at the end of the top rows. This design can be extended to any number of bits, but practical limitations due to timing considerations restrict the use of more than a byte or so. The outputs are triggered by the inputs 11, 01, 00, 10, respectively.

Logic unit 3

Arithmetic logic unit (ALU)

ALUwikipedia

The Arithmetic logic unit (ALU) is the central part of the CPU. It does calculations and logical processing and then passes this information to a register. The ALU, on basis of the input, selects a specific function, performs it, and then gives the result.

The ALU shown below is a 1-bit ALU with the functions: ADD, AND, XOR. It takes the A and B inputs and then performs the selected functions. Read about the adders to see how the ADD function works. XOR and AND are basic functions that are explained on the logic circuits page. There can be more functions added to an ALU, like multiplication, division, OR, NAND... etc. These functions could, with some modifications, be added to this 1 bit ALU.

This 1-bit ALU can be linked to each other to create an as many bit ALU as possible. Just like adders you need to connect the Carry out (Cout) to the Carry in (Cin) of the next ALU

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