User:L4bbogdanbarbu/Computer

The following is a digital redstone computer. It is a RISC architecture designed to be simple to understand and implement. It's relatively fast but it's still running in Minecraft so don't expect any miracles. Obviously, improvements are possible but I aimed at keeping things clean.

A monitor is planned for a future article (since it has other applications as well).

Bus
A bus is responsible for transmitting bits from one component of a system to another. It is implemented using redstone and redstone repeaters, as required. However, care needs to be taken in order to ensure that the delays added by the repeaters are accounted for. A computer needs synchronization.

Memory
There are three separate address spaces: one for code, one for processes to use, and the other for I/O.

ROM
The computer uses the stored program concept. Programs are stored in ROM, in an address space which is unavailable to running processes. Once the computer is turned on, instructions are fed to the CPU one at a time, in order. The instructions are encoded in a series of levers, each one representing a bit.

RAM
This computer's main memory is implemented using an array of latches. The latches appear in groups of 8, yielding bytes. They're also are connected to a memory controller which can read a byte from specified address and send it to the CPU or be told by the CPU to write a byte to a particular address.

Latch
Latches can be used to store bits. Here is the circuit schematic for the latch type used in this computer:

The inputs S and C are used to set and clear the bit, respectively. Thus, the convention is that a redstone signal represents 1 and lack thereof represents 0.

I/O
I/O is essentially like main memory, except peripherals may be connected to its latches via a bus, to either read or write. Examples of peripherals include keyboards, monitors, networks, sensors, and actuators.

Logic gates
Logic gates implement boolean functions, which will become useful in actually implementing our instructions. Several types are often useful:

NOT Gate
This is just a torch inverter.

Structure size: 1 &times; 4 &times; 1

Circuit delay: 1 redstone tick

AND Gate
Structure size: 3 &times; 6 &times; 2

Circuit delay: 2 redstone ticks

OR Gate
Structure size: 2 &times; 3 &times; 1

Circuit delay: 0 redstone ticks

NAND Gate
NAND gates are functionally complete, meaning that they can be used to simulate any other type of logic gate.

Structure size: 3 &times; 4 &times; 1

Circuit delay: 1 redstone tick

NOR Gate
NOR gates are functionally complete, meaning that they can be used to simulate any other type of logic gate.

Structure size: 3 &times; 4 &times; 1

Circuit delay: 1 redstone tick

XOR Gate
Structure size: 4 &times; 5 &times; 1

Circuit delay: 1 redstone tick

ISA
Instructions are fed from the ROM where they are encoded as 4-byte words. This is to accomodate the following encoding while keeping things simple:

That's one instruction, the addresses of two operands, and the address where the result is to be stored. Not all instructions will have this format, of course, but this is what influenced the design.

Numerical values use the two's complement representation.

Clock
To start the clock, a short pulse is required.

Interrupts
Peripherals may want to trigger one of the interrupt pins in order to signal that information of some sort has become available, perhaps in the I/O address space.