User:Depressed pho/Thyristor

These are a little like D flip-flops but have a different functionality. They have two inputs just like a D flip-flop: the data line D and the "clock" input C. When trigerred by C, the circuits set its output (Q) to D only if D is high, then hold that output state until D goes low. Otherwise Q stays low. ''The author of this article doesn't know its common name. They even don't know whether it has a name.''

Schematic
Design A is the simplest form of the circuit. The hopper is initially empty so Q stays low regardless of whether D is high or low. But when C goes high, the item in the dropper gets moved to the hopper so Q goes high as well. The hopper is suspended by D so as long as D is high, the item won't go back to the dropper so Q is kept high. ''But there is a downside to this design. When C is activated while D is low, a 1 tick on-pulse gets emitted from the output.''

Design B is an improved form at the cost of complexity / size / delay. There is an AND gate between C and D so the clock input gets completely discarded when D is low.